The present invention relates to a magnetoresistive effect element and a memory device using the same.
Magnetoresistive effect elements are used for various applications, such as memory devices such as MRAM (Magnetic Random Access Memory), magnetic heads of hard disk drives (HDD), magnetic sensors, and so on. Of such magnetoresistive effect elements, TMR (Tunneling Magneto-Resistive effect) elements which are one kind of magnetoresistive effect elements each allowing a sensing current to flow in a direction perpendicular to the laminated surface of the TMR element have come to be used for various applications because of their high MR (Magneto-Resistance) ratio.
On the other hand, MRAM is nonvolatile and capable of solving the volatility which is one of drawbacks of DRAM (Dynamic Random Access Memory) used heretofore. Thus, researches on MRAM have been advanced.
Here, two examples of MRAMs using TMR elements in the background art will be described with reference to the drawings.
First, a first conventional example will be described with reference to FIG. 39. FIG. 39 is a schematic sectional view showing the vicinity of one memory cell of an MRAM in the first conventional example. The MRAM has a plurality of upper conductor wires 1 and a plurality of lower conductor wires 2. The upper conductor wires 1 are disposed at intervals in the direction perpendicular to the paper of FIG. 39 so as to extend in the left/right direction in FIG. 39. The lower conductor wires 2 are disposed at intervals in the left/right direction in FIG. 39 so as to extend in the direction perpendicular to the paper of FIG. 39. TMR elements 3 are disposed as memory cells at the crossing points of the wires 1 and 2 respectively. Each TMR element 3 is constituted by a tunnel barrier layer 4 made from an insulating layer, two magnetic layers 5 and 6 having the tunnel barrier layer 4 put therebetween, and a pin layer 7 made from an antiferromagnetic layer. The direction of magnetization of the lower magnetic layer 6 is fixed by the pin layer 7 so that the magnetic layer 6 serves as a pinned layer. On the other hand, the upper magnetic layer 5 serves as a free layer whose magnetization direction is variable in accordance with an external magnetic field. The upper magnetic layer 5 is electrically connected to the corresponding upper conductor wire 1, and the pin layer 7 is electrically connected to the corresponding lower conductor wire 2.
In this first conventional example, each memory cell is constituted by one TMR element 3. Then, each TMR element 3 has only one overlapping area (tunnel junction area) of the tunnel barrier layer 4 with the two magnetic layers having the tunnel barrier layer 4 put therebetween.
When data is written into the TMR element 3, the direction of magnetization in the free layer 5 is established by a combined current magnetic field of magnetic fields generated by currents applied to the upper conductor wire 1 and the lower conductor wire 2 connected to the TMR element 3. When the direction of one of the currents applied to the wires 1 and 2 is changed, the direction of magnetization in the free layer 5 can be switched between parallelism and antiparallelism to the direction of magnetization in the pinned layer 6.
The TMR element 3 has the property that the resistance value of a current flowing from one of the magnetic layers 5 and 6 to the other thereof through the tunnel barrier layer 4 becomes low (R) when the directions of magnetization in the magnetic layers 5 and 6 are parallel (identical), while the resistance value becomes high (R+ΔR) when the directions of magnetization are antiparallel. Accordingly, a set of data “0” and “1” (or the reverse of them) can be stored correspondingly to resistance values R and R+ΔR respectively. Incidentally, the ratio ΔR/R in this event is the MR radio of the TMR element 3. When data is read out, a current (sensing current) is allowed to flow in the course from the upper wire layer 1 to the lower wire layer 2 through the respective layers 5, 4, 6 and 7 (or in the reverse course). The magnitude of the resistance value is detected based on this current, so as to read the data written in the TMR element 3.
As is understood from the above description, not only when data is written but also when data is read, one of the plurality of upper conductor wires 1 is selected and one of the plurality of lower conductor wires 2 is selected. Thus, a specific TMR element 3 (memory cell) is selected, and data is written/read into/from the selected TMR element 3.
Incidentally, a layer 8 includes circuit element constituent parts, wiring and so on for forming circuits for performing writing and reading thus, together with a semiconductor substrate 9. The details of the layer 8 are not shown in FIG. 39. The TMR elements 3 and the conductor wires 1 and 2 are formed on the semiconductor substrate 9 and the layer 8. The semiconductor substrate 9 and the layer 8 correspond to a so-called IC substrate as a whole.
MRAM corresponding to the first conventional example described above is disclosed in Patent Document 1.
Next, MRAM according to a second conventional example will be described with reference to FIGS. 40 and 41. FIG. 40 is a circuit diagram showing a reading circuit of the MRAM according to the second conventional example. FIG. 41 is a sectional view showing the structure of the reading circuit. This second conventional example shows the MRAM disclosed in Patent Document 2. In this MRAM 100, one TMR element is used as each memory cell. TMR elements (magnetic laminates each having a tunnel junction) MS0 to MS3 are electrically connected in series, and transistors X0 to X3 are electrically connected to the TMR elements MS0 to MS3 through vias VU1, VL1, VU2, VL2 and VU3 respectively. One end of the series connection of the TMR elements MS0 to MS3 is connected to a bit line BL through a switch S1, and the other end thereof is grounded. Incidentally, in FIG. 41, the reference numerals 108, 110, 112, 114, 116 and 118 represent source/drain regions (+n regions) for forming the switch S1 and the transistors X3 to X1, and the signs PC represent gates for forming the switch S1 and the transistors X3 to X1. In addition, the reference numerals 120, 122, 124, 126 and 128 represent metal plates.
The principle of reading/writing data in this second conventional example is fundamentally similar to that in the first conventional example. In the second conventional example, however, writing data is performed by use of a combined current magnetic field between a bit line BL disposed above the TMR elements MS0 to MS3 so as to be shared among the TMR elements MS0 to MS3 and a word line WL selected from word lines WL provided under the TMR elements MS0 to MS3 in one-to-one correspondence. On the other hand, reading data is performed as follows. That is, only one of the transistors X0 to X3 is turned off selectively while the other transistors are turned on. Then, the switch S1 is turned on so that the TMR element corresponding to the transistor turned off selectively is selected. Reading data is performed based on a current outputted from the selected TMR element.
In the second conventional example, each memory cell is constituted by one TMR element in the same manner as in the first conventional example. In addition, each TMR element has only one overlapping area (tunnel junction area) of the tunnel barrier layer with the two magnetic layers having the tunnel barrier layer put therebetween.
The second conventional example is superior to the first conventional example in terms of increase in memory capacity. That is, the structure of a memory device according to the first conventional example is generally called an NOR circuit, which is regarded as a circuit configuration suitable for high-speed memory operation. However, such a structure has a drawback in complicated wiring. Thus, the structure is not suitable for increasing in memory capacity. A large number of address control lines are required for designating an individual address. Thus, there is a drawback that the way to designate the address is complicated. On the other hand, the second conventional example adopts the circuit configuration for the reading circuit. The circuit is referred to as a so-called NAND circuit. Accordingly, due to the drain/source shared among the transistors X0 to X3, it is not necessary to provide wiring of a special conductor pattern as the wiring among the transistors. Thus, the density in transistor arrangement can be improved, and hence the memory capacity can be increased.
[Patent Document 1]Japanese Patent Laid-Open No. 2002-249565
[Patent Document 2]U.S. Patent Application Publication No. 2002/0097598
However, in a general TMR element as adopted in the first and second conventional examples, there is a drawback that the MR ratio obtained actually is reduced due to the voltage bias characteristic possessed by the TMR element. This drawback will be described.
To read data or perform another magnetic detection in a TMR element, it is necessary to allow a sensing current to flow between two magnetic layers (two magnetic layers having a tunnel barrier layer put therebetween) of the TMR element. Therefore, a voltage is applied between the two magnetic layers so as to allow the current to flow therebetween. However, the rate of change in magnetic resistance (MR ratio ΔR/R) of the TMR element is generally not so high, that is, not higher than 50%. In addition, the TMR element has the characteristic (voltage bias characteristic) that the MR ratio is reduced with the increase of the voltage applied to allow a current to flow in the laminated direction of the TMR element. Though the change of the MR ratio depends on the configuration of the TMR element, for example, the MR ratio becomes approximately not higher than half of the aforementioned value when the voltage applied is increased to about 0.5 V.
Thus, in the first and second conventional examples, the S/N ratio of a read signal is lowered so that the reliability in reading data cannot be always enhanced satisfactorily.
Improvement in MR ratio is the most important problem not only when TMR elements are used in an MRAM but also when TMR elements are used in a magnetic head, a magnetic sensor or the like.
In addition, in the second conventional example, it is essential to electrically connect both the input and output terminals (where a sensing current flows in and out) of each TMR element to the substrate side when an NAND circuit is adopted as a reading circuit. In the second conventional example, the substrate-side end portions of the TMR elements MS0 to MS3 are connected to the substrate through the vias VL1 and VL2 while the other end portions of the TMR elements MS0 to MS3 opposite to the substrate are connected to the substrate through the vias VU1, VU2 and VU3. However, since a sensing current must be allowed to flow into the tunnel junction area of each TMR element perpendicularly to the laminated surface of the TMR element, it is inevitable to leave one end portion of the TMR element MS0-MS3 at a distance from the substrate relatively to the other end portion. Thus, in comparison with the vias VL1 and VL2, the vias VU1, VU2 and VU3 have to be formed to be higher in height so as to extend over a larger number of layers. However, it is difficult in a manufacturing process to form each via extending over a large number of layers.
As described above, the second conventional example is indeed suitable for increasing the memory capacity, but it is not possible to make the manufacturing process easy.
Although description has been made here on the second conventional example, also in various applications using magnetoresistive effect elements each allowing a sensing current to flow perpendicularly to the laminated surface of the magnetoresistive effect element, it is often necessary to connect the input and output terminals of each magnetoresistive effect element to the substrate side. In such a case, the manufacturing process cannot be made easy for the same reason as in the second conventional example.